This invention relates, in general, to the processing of semiconductor devices and, more particularly, to a novel process for forming closely spaced conductive lines.
As the density of integrated circuit devices formed within a given chip size is increased, the prior art has found that a significant saving in space may be realized by, for example, reducing the size of the areas required for buried contacts. With this reduction in size of the buried contact areas, the space previously occupied by the buried contact may be used for the formation of additional devices. Further, while line widths have also been reduced to the micron and submicron level in an attempt to provide more useful area, it has rapidly reached the point where other means must be utilized to make more area available for the formation of additional devices.
One obvious advantage to having closely spaced lines resides in the Charge Coupled Device (CCD) art wherein the closely spaced lines afford higher transfer efficiencies and higher packing densities. However, there are practical manufacturing limitations as to how closely the lines can be space one from the other. To overcome this difficulty the art resorts to forming a plurality of widely spaced lines, covering the widely spaced lines with a layer of an insulating oxide and thereafter inserting interdigitated lines in the insulated spaces between the first mentioned lines. However, in an arrangement such as this, the interdigitated lines usually overlap the previously formed lines. Thus, it would be advantageous to devise a processing scheme to produce narrow gaps between conductive lines without having to resort to a multilevel interdigitated line technique now used by the prior art.
Another art area that would benefit from close line or electrode spacing is in the self-aligned SOS MESFET art. In these devices, if either of the source or drain diffusion regions were to touch the gate electrode, the gate would be shorted and the Schottky barrier would be lost. However, the greater the separation of the source and drain diffusion regions from the gate member, the higher the channel resistance will be. Thus, with close spacing between the diffusion regions and the gate member, the channel resistance will be optimized. Additionally, with such a fixed minimum geometry, the overall size of the silicon island would be significantly reduced, thereby achieving additional area for additional devices.